1. Field of the Invention
The present invention relates to an apparatus and method for memory migration in a distributed memory multiprocessor system.
2. Description of the Related Art
A technique for memory migration in a distributed memory multiprocessor system is disclosed in Japanese Patent Laid-Open No. 2004-054931 (Hereinafter, “Patent Document 1”). The related art will be described below with reference to the drawings.
FIG. 8 shows a configuration of a distributed memory multiprocessor system according to the related art.
The system includes four cells 510, 512, 514, 516, which are interconnected through inter-cell networks 580 and 582. The cell 510 includes two processors 520A and 520B, which are connected to caches 530A and 530B, respectively. The cell 510 further includes a memory controller 550 connected to a memory 560 and a directory 570. An intra-cell network 540 interconnects the caches 530A, 530B, the memory controller 550, and the inter-cell network 580.
In order to ensure that the latest data in the system is provided in response to access from a processor to any address, cache coherency control is performed. To implement the cache coherency control, directory information is stored in the directory on a line by line basis, where a line is a unit to be fetched from a cache. The directory information includes a bitmap indicating which cell's cache holds data and a clean bit indicating whether the data in the memory is the latest data. Here, the directory information for data stored in the memory 560 is held in the directory 570 in the same cell 510.
When migrating from the memory 560 in the cell 510 to the memory 562 in another cell 512 in the system, the cell 510 is referred to as the old cell 510 and the cell 512 is referred to as new cell 512. FIG. 9 shows details of that the memory controller 552 for the new cell 512. FIG. 10 shows details of the memory controller 550 for the old cell 510.
The memory controller 552 of the new cell 512 has a fetch requesting unit 5521 and a memory data updating unit 5522. The memory controller 550 of the old cell 510 has an invalidating unit 5501 and data transmitting unit 5502.
The flowchart in FIG. 11 shows the operation of migrating one line of data from the memory 560 of the old cell 510 to the memory 562 of the new cell 512 in the system.
At step S501, the fetch requesting unit 5521 of the memory controller 552 of the new cell 512 sends to the old cell 510 a fetch request to fetch a line to be migrated. At step S503, the invalidating unit 5501 of the memory controller 550 of the old cell 510 receives the fetch request and performs a process for invalidating the line of data held in a cache in the system in accordance with information stored in the directory 570. After the invalidating process performed at step S503 is completed, the data transmitting unit 5502 of the memory controller 550 transmits the line of data to the new cell 512 at step S505. At step S507, the memory data updating unit 5522 of the memory controller 552 of the new cell 512 which received the data updates the memory 562. Here, the information stored in the directory 572 is initialized to a state indicating that none of the caches in the cells hold data and the latest data is contained in the memory.
Once the process described above is completed, an access request to the line is redirected from the old cell 510 to the new cell 512 and the information stored in the directory 572 of the new cell 512 indicates that none of the caches of the cells hold data and the latest data is contained in the memory. Therefore, the line can be migrated from the old cell 510 to the new cell 512 while coherency is maintained.
In the related art, when data is transferred from the old cell to the new cell with the memory migration, the cache holding the line in the multiprocessor system is invalidated. Therefore, the related art has a problem that a cache miss occurs in the processor that was accessing the old line, leading to performance deterioration.